library verilog;
use verilog.vl_types.all;
entity Permuted_Choice_2 is
    port(
        Permuted_Choice_2_Input: in     vl_logic_vector(56 downto 1);
        Permuted_Choice_2_Select: in     vl_logic;
        Permuted_Choice_2_Output: out    vl_logic_vector(48 downto 1);
        Permuted_Choice_2_Finish_Flag: out    vl_logic;
        clk             : in     vl_logic
    );
end Permuted_Choice_2;
